Sequential delay test techniques are widely used for test and measurement involving timing parameters and stimuli. A technique is to launch a transition, (step, edge and/or pulse) at the input of a circuit and subsequently capture particular output(s) at a known time after the launch. A number of such tests may be combined to characterize a circuit's step response. Delays between launch and corresponding capture events are preferably programmable with a desired measurement resolution. For example, for basic I/Os (input-output circuits), it may typically be desirable to generate strobes whose relative delay can be programmed from roughly 0 to 10 ns (nanoseconds) with resolution of 100 ps (picoseconds) or better.
Some methods for programmable delay strobe generation may use excessively large numbers of delay circuit elements, or delay control taps to achieve sufficient performance. Also, in some implementations, an excessively high degree of device matching and/or calibration may be desirable.
Usage of DLL (delay-locked loop) circuits in digital signal generators may provide superior noise immunity, stability and relaxed settling performance. On the other hand, DLLs may require good tolerance delay elements that are not cheap in terms of semiconductor real-estate or manufacturing costs. Where timing tests, such as I/O timing tests are to be performed on a device in embedded mode (using mostly self-generated signals). It is particularly important that the circuitry provide good performance without large real estate requirements such as may arise out of excessive circuit complexity.